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Connection between FPGA and PC using UDP/IP core
by linch on May 23, 2014 |
linch
Posts: 1 Joined: May 14, 2014 Last seen: Jun 6, 2014 |
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Hello,
I am going to make connection between FPGA(virtex-6) and PC(linux) via emac. I use the UDP/IP core and look through the paper (by Alachiotis., etc.) in the doc/. This paper mentioned that "a respective ARP cache entry must be added manually, every time the connection is reset". Does that mean I should execute the file "setup.sh"(in the JAVA_app/ folder), when I want to reset the connection? Thank you in advance. |
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RE: Connection between FPGA and PC using UDP/IP core
by onkelzfan on Jun 6, 2014 |
onkelzfan
Posts: 1 Joined: Mar 28, 2011 Last seen: Sep 12, 2014 |
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Hi,
I try to do the same at the moment. If you open the setup.sh file, you will see that it is only configuring your Linux PC ethernet connection. The ethernet connection of the FPGA is defined in definition2_ipv4_lut.coe. The order of the bytes is shown in README.txt. If you get it to work, please reply ;) |
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